With the increasing complexity of microprocessor and system-on-chip (SOC) design, more and more attention is being paid to improving the processes of generating and verifying circuit design constraints. Manual processes for creating design constraints for physical composition and verification of the constraints are becoming infeasible on designs with extensive clock gating and multiple clock and power domains. Tools have attempted to automate the process of constraints generation and other tools have attempted to automate the process of constraints verification. However, these attempts have had limited success.
One challenge facing these tools is that of understanding all the different design varieties. Previous tools generated a small subset of design constraints from typical pre-existing designs that were known, and yet still required heavy manual involvement by circuit designers to determine the rest of the constraints. Verification of design constraints is handled separately and independently by other different tools and is performed subsequently at the later stages of the design process. Inconsistency between constraints applied to the physical implementation and constraints verified in the verification flow is a significant issue. For example, constraints such as multi-cycle paths applied to the timing analysis in the physical flow may not be verified in the verification flow due to the usage of different tools that operate independently. The independent tools also caused certain components to not be checked during verification such as missing level-shifters between different power domains.